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TC55VDM518AFFN22/20/16/15
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
36M 3.3V Pipelined NtRAMTM 2M Word by 18Bit SYNCHRONOUS NO-TURNAROUND STATIC RAM DESCRIPTION
The TC55VDM518AFFN is a synchronous static random access memory (SRAM) organized as 2,097,152 words by 18 bits. NtRAMTM(no-turnaround SRAM) offers high bandwidth by eliminating dead cycles during the transition from a read to a write and vice versa. All inputs except Output Enable OE and the Snooze pin ZZ are synchronized with the rising edge of the CLK input. A Read operation is initiated by the ADV Address Advanced Input signal ; the input from the address pins and all control pins except the OE and ZZ pins are loaded into the internal registers on the rising edge of CLK in the cycle in which ADV is asserted. The output data is available two clock cycles later. Write operations are internally self-timed and are initiated by the rising edge of CLK in the cycle in which ADV is asserted. The input from the address pins and all control pins except the OE and ZZ pins are loaded into the internal registers on the rising edge of CLK in the cycle in which ADV is asserted. Input data is loaded in the third cycle after the cycle in which ADV is asserted. Byte Write Enables ( BW1 to BW2 ) allow from one to four Byte Write operations to be performed. A 2-bit burst address counter and control logic are integrated into this SRAM. The TC55VDM518AFFN uses a single power supply (3.3 V) or dual power supplies (3.3 V for core and 2.5 V for output buffer) and is available in a 100-pin low-profile plastic QFP (LQFP).
FEATURES
* * * * * * * Organized as 2,097,152 words by 18 bits No-turnaround operation with pipeline data output 2-bit burst address counter (support for interleaved or linear burst sequences) Synchronous self-timed Write Byte Write control Snooze mode pin (ZZ) for power down LVTTL-compatible interface * Single 3.3V 5% power supply VDD * Dual 3.3 V or 2.5 V power supply VDDQ * Available in 100-pin LQFP package (LQFP100-P-1420-0.65B ; weight : (typical))
Clock Cycle Time Clock Access Time Operating Current tKC tKQV IDDO1 225 4.4 2.8 200 167 5.0 6.0 3.2 3.5 TBD
grams
150 6.6 3.8
MHz
ns ns mA
PIN ASSIGNMENT (TOP VIEW)
A6 A7 /CE CE2 NC NC /BW2 /BW1 /CE2 VDD VSS CLK /WE /CKE /OE ADV A19 A17 A8 A9
PIN NAMES
CLK A0 to A20 Clock Input Address Inputs
NC NC NC VDDQ VSSQ
NC
NC I/O9 I/O10 VSSQ VDDQ I/O11 I/O12 VDD VDD VDD VSS I/O13 I/O14 VDDQ VSSQ I/O15 I/O16 I/OP2 NC VSSQ VDDQ NC NC
NC
99 97 95 93 91 89 87 85 83 81 1 2 100 98 96 94 92 90 88 86 84 82 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 32 34 36 38 40 42 44 46 48 50 30 31 33 35 37 39 41 43 45 47 49 MODE A5 A4 A3 A2 A1 A0 NU NC VSS VDD NC A20 A10 A11 A12 A13 A14 A15 A16
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A18 NC NC VDDQ VSSQ
CE , CE2 , CE2 Chip Enable Inputs OE WE BW1 to BW2
Output Enable Input Write Enable input Byte Write Enable Address Advance Input Clock Enable Snooze Input Data Inputs/Outputs Parity Data Inputs/Outputs Mode select Input No Connection Not Usable Power Supply for Core Power Supply for Output Buffer Ground for Core Ground for Output Buffer
NC
I/OP1 I/O8 I/O7 VSSQ VDDQ I/O6 I/O5 VSS VDD VDD ZZ I/O4 I/O3 VDDQ VSSQ I/O2 I/O1 NC NC VSSQ VDDQ
ADV
CKE
ZZ I/O1 to I/O16 I/OP1 to I/OP2 MODE NC NU VDD VDDQ VSS VSSQ
TM
NC
NC NC
Note : NtRAM and No-Turnaround Random Access Memory are trademarks of Samsung Electronics Co., Ltd..
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BLOCK DIAGRAM
21 A0 to A20 Address Register A0 / A1 Binary Counter and Logic 21 Address Register 2 Memory Cell Array 2 M x 18 bits (37,748,736 bits)
MODE
18
18
Address Register 1
Output Register
ADV
BW1 to BW2 WE
Din Register 2 Read/Write Control Logic & Coherency Control Logic Din Register 1 18 Data-Out Control Data-Out Control 18
CLK
CKE
CE CE2 CE2
OE
I/O, I/OP
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PIN DESCRIPTIONS
PIN NUMBER SYMBOL TYPE DESCRIPTION Clock Input All synchronous input signals are registered on the rising edge of CLK. When the chip is enabled, address inputs and control pins except for OE and ZZ must meet the specified setup and hold times with respect to the CLK rising edge. Address Inputs These address inputs are registered on the rising edge of CLK. When the chip is enabled, address inputs must meet the specified setup and hold times with respect to the CLK rising edge. Chip Enable Input This active-Low signal controls the chip status (enabled or disabled). It is sampled only when a new external address is loaded. Chip Enable Input This active-Low signal controls the chip status (enabled or disabled). It is sampled only when a new external address is loaded. Chip Enable Input This active-High signal controls the chip status (enabled or disabled). It is sampled only when a new external address is loaded. Output Enable Input This active-Low signal controls all 18 bits of the I/O output buffer. Write Enable Input This active-Low input controls Read/Write operations. Byte Write Enable These active-Low inputs control Byte Write operations when a Write cycle is active. A Byte Write pin controls I/O pins as follows. BW1 : I/O1 to I/O8, I/OP1 BW2 : I/O9 to I/O16, I/OP2 Address Advance Input This is used to load the internal registers with the input from the address and control signals when it is Low on the rising edge of CLK. When it is High, the internal burst address counter is incremented. The external address inputs are ignored when this signal is High. Clock Enable When High, CLK input is ignored and outputs retain the same state. Snooze Input This active-High signal is used to place the device into Sleep Mode (Low-Power Standby Mode). When Low, the device remains in the Active state. When High, the device goes into the Sleep state and memory data is retained. After this signal has been de-asserted, the device will wake up when a read or write operation is initiated by ADV.
89
CLK
Input (NA)
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, A0 to A20 48, 49, 50, 83,80,84,43
Input (synchronous)
98
CE
Input (synchronous)
92
CE2
Input (synchronous)
97
CE2
Input (synchronous)
86
OE
Input (asynchronous) Input (synchronous)
88
WE
93, 94
BW1 to BW2
Input (synchronous)
85
ADV
Input (synchronous)
87
CKE
Input (synchronous)
64
ZZ
Input (asynchronous)
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PIN NUMBER
SYMBOL
TYPE
DESCRIPTION
58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, 18, 19, 22, I/O1 to I/O16 23
I/O (synchronous)
Data Input/Output
74,24
I/OP1 to I/OP2
I/O (synchronous)
Parity Data Input/Output
31
MODE
Input (synchronous)
Mode Select Input This signal selects the burst sequence. When High, the burst sequence is interleaved. When Low, it is linear.
1,2,3,6,7,25,28,29,30,39, 42,51,52,53,56,57,75,78, 79,95,96
NC
NC
Not Connected
38
NU
Input (asynchronous) Supply
Not Usable
14, 15, 16, 41, 65, 66, 91
VDD
Power Supply for Core
4, 11, 20, 27, 54, 61, 70, VDDQ 77 17, 40, 67, 90 VSS
Supply
Power Supply for Output Buffers
Ground
Ground for Core
5, 10, 21, 26, 55, 60, 71, VSSQ 76
Ground
Ground for Output Buffers
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OPERATING MODE
(1) Synchronous Input Truth Table
OPERATION Read (begin burst) Read (continue burst) Write (begin burst) Write (continue burst) NOP/Write Abort (begin burst) Write Abort (continue burst) Deselected Deselect Continue (Note 2) Ignore Clock Edge (Note 3) Snooze
WE
ADV L H L H L H L H X X
CE Select X Select X Select X Deselect X X X
BW
Addr. Used External Internal External Internal X Internal X X X X
CKE
ZZ L L L L L L L L L H
I/O (2 cycles later) Output Output Input Input Hi-Z Hi-Z Hi-Z Hi-Z Previous value Hi-Z
H X L X L X X X X X
X X L L H H X X X X
L L L L L L L L H X
Notes: 1. H means logical High and L means logical Low. X means Don't care. 2. A Deselect Continue cycle can only be entered if a Deselect cycle is executed before it. 3. When the Ignore Clock Edge command is asserted during a Read operation, the output data for the previous cycle still appear on the I/O pins. When the command is asserted during a Write operation, the I/O pins remain at Hi-Z and the Write operation is not executed. 4. All synchronous Inputs must exhibit adequate setup and hold times either side of the rising edge of the CLK pin. 5. ZZ input is asynchronous, but is included is this table.
(2) Write Enable Truth Table
OPERATION Read
WE
BW1 BW2
I/O1 to I/O8 I/OP1 Output Input Input Hi-Z Hi-Z
I/O9 to I/O16 I/OP2 Output Input Hi-Z Input Hi-Z
H L
X L L H H
X L H L H
Write
L L L
Notes: 1. H means logical High and L means logical Low. X means Don't care. 2. The status for I/O pins described in this column appears two clock cycles after the cycle in which the Read or Write command is asserted.
(3) Asynchronous Inputs Truth Table
OPERATION Read Write Stop clock (Note 2) Snooze (Note 3) Notes: 1. 2. 3. 4. 5.
OE
ZZ L L L L L H
I/O Dout Hi-Z Din, Hi-Z Hi-Z Low-Z Hi-Z
L H X H L X
H means logical High and L means logical Low. X means Don't care. The Stop CLK Mode achieves Low-Power Standby by stopping the input clock. The Snooze Mode achieves Low-Power Standby by asserting the ZZ pin. The cycle immediately prior to a Snooze brought about by the ZZ pin must be a Read Mode or Deselect Mode cycle. Memory data is retained during Snooze Mode cycles.
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(4) Burst Sequence
MODE PIN L H or NC BURST OPERATION Linear burst order Interleaved burst order
a) Linear Burst Sequence (MODE input = VSS)
Bit Order : A20 - - - - - - - - - - A1 A0
1st Address (external) XX - - - - - - XX00 XX - - - - - - XX01 XX - - - - - - XX10 XX - - - - - - XX11 2nd Address (internal) XX - - - - - - XX01 XX - - - - - - XX10 XX - - - - - - XX11 XX - - - - - - XX00 3rd Address (internal) XX - - - - - - XX10 XX - - - - - - XX11 XX - - - - - - XX00 XX - - - - - - XX01 4th Address (internal) XX - - - - - - XX11 XX - - - - - - XX00 XX - - - - - - XX01 XX - - - - - - XX10
b) Interleaved Burst Sequence (MODE input = VDD or NC)
Bit Order : A20 - - - - - - - - - - A1 A0
1st Address (external) XX - - - - - - XX00 XX - - - - - - XX01 XX - - - - - - XX10 XX - - - - - - XX11 2nd Address (internal) XX - - - - - - XX01 XX - - - - - - XX00 XX - - - - - - XX11 XX - - - - - - XX10 3rd Address (internal) XX - - - - - - XX10 XX - - - - - - XX11 XX - - - - - - XX00 XX - - - - - - XX01 4th Address (internal) XX - - - - - - XX11 XX - - - - - - XX10 XX - - - - - - XX01 XX - - - - - - XX00
DEVICE OPERATION
(1) Read Operation
CYCLE n n+1 n+2 ADDRESS A0 X X
WE BW
ADV L X X
CE
OE
CKE
I/O X X Q0
OPERATION Address & control valid
H X X
X X X
L X X
X X L
L L X
Read out A0
Notes: 1. H means logical High and L means logical Low. X means Don't care. Q is data output.
(2) Burst Read Operation
CYCLE n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n + 10 ADDRESS A0 X X X X A1 X X A2 A3 X
WE BW
ADV L H H H H L H H L L X
CE
OE
CKE
I/O X X Q0
OPERATION Address & control valid
H X X X X H X X H H X
X X X X X X X X X X X
L X X X X L X X L L X
X X L L L L L L L L L
L L L L L L L L L L L
Read out A0
Q0 + 1 Read out A0 + 1 Q0 + 2 Read out A0 + 2 Q0 + 3 Read out A0 + 3 Q0 Q1 Read out A0 Read out A1
Q1 + 1 Read out A1 + 1 Q1 + 2 Read out A1 + 2 Q2 Read out A2
Notes: 1. H means logical High and L means logical Low. X means Don't care. Q is data output.
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(3) Write Operation
CYCLE n n+1 n+2 ADDRESS A0 X X
WE BW
ADV L X X
CE
OE
CKE
I/O X X D0
OPERATION Address & control valid
L X X
L X X
L X X
X X X
L L L
Write to A0
Notes: 1. H means logical High and L means logical Low. X means Don't care. D is data input.
(4) Burst Write Operation
CYCLE n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n + 10 ADDRESS A0 X X X X A1 X X A2 A3 X
WE BW
ADV L H H H H L H H L L X
CE
OE
CKE
I/O X X D0 Write A0
OPERATION Address & control valid
L X X X X L X X L L X
L L L L L L L L L L L
L X X X X L X X L L X
X X X X X X X X X X X
L L L L L L L L L L L
D0 + 1 Write A0 + 1 D0 + 2 Write A0 + 2 D0 + 3 Write A0 + 3 D0 D1 Write A0 Write A1
D1 + 1 Write A1 + 1 D1 + 2 Write A1 + 2 D2 Write A2
Notes: 1. H means logical High and L means logical Low. X means Don't care. D is data input.
(5) Read Operation with Clock Enable
CYCLE n n+1 n+2 n+3 n+4 n+5 n+6 n+7 ADDRESS A0 X A1 X X A2 A3 X
WE BW
ADV L X L X X L L X
CE
OE
CKE
I/O X X X Q0 Q0 Q0 Q1 Q2
OPERATION Address & control valid Ignore cycle Address & control valid Ignore clock, Q0 is on bus Ignore clock, Q0 is on bus Read out A0 Read out A1 Read out A2
H X H X X H H X
X X X X X X X X
L X L X X L L X
X X X L L L L L
L H L H H L L L
Notes: 1. H means logical High and L means logical Low. X means Don't care. Q is data output.
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(6) Write Operation with Clock Enable
CYCLE n n+1 n+2 n+3 n+4 n+5 n+6 n+7 ADDRESS A0 X A1 X X A2 A3 X
WE BW
ADV L X L X X L L X
CE
OE
CKE
I/O X X X X X D0 D1 D2
OPERATION Address & control valid Ignore clock Address & control valid Ignore clock Ignore clock Address & control valid Write A1 Write A2
L X L X X L L X
L X L X X L L X
L X L X X L L X
X X X X X X X X
L H L H H L L L
Notes: 1. H means logical High and L means logical Low. X means Don't care. D is data input.
(7) Read Operation with Chip Enable
CYCLE n n+1 n+2 n+3 n+4 n+5 n+6 n+7 ADDRESS A0 X A1 X X A2 X X
WE BW
ADV L L L L L L L L
CE
OE
CKE
I/O X X Q0 Z Q1 Z Z Q2
OPERATION Address & control valid Deselect Read A0 Deselect Read A1 Deselect Deselect Read A2
H X H X X H X X
X X X X X X X X
L H L H H L H H
X X L X L X X L
L L L L L L L L
Notes: 1. H means logical High and L means logical Low. X means Don't care. Q is data output. Z means Hi-Z.
(8) Write Operation with Chip Enable
CYCLE n n+1 n+2 n+3 n+4 n+5 n+6 n+7 ADDRESS A0 X A1 X X A2 X X
WE BW
ADV L L L L L L L L
CE
OE
CKE
I/O X X D0 Z D1 Z Z D2
OPERATION Address & control valid Deselect Write A0 Deselect Write A1 Deselect Deselect Write A2
L X L X X L X X
L X L X X L X X
L H L H H L H H
X X X X X X X X
L L L L L L L L
Notes: 1. H means logical High and L means logical Low. X means Don't care. D is data input. Z means Hi-Z.
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MAXIMUM RATINGS
SYMBOL VDD VDDQ VIN VI/O PD Tsolder Tstg Topr Power Supply Voltage Output Buffer Power Supply Voltage Input Terminal Voltage Input/Output Terminal Voltage Power Dissipation Soldering Temperature (10s) Storage Temperature Operating Temperature RATING VALUE -0.5 to 4.6 -0.5 to VDD + 0.5 ( 4.6 V max) -0.5* to 4.6 -0.5* to VDDQ + 0.5** ( 4.6 V max) 1.5 260 -65~150 -10~85 UNIT V V V V W C C C
*: -1.0 V with a pulse width of 20% of tKC min (3 ns max) **: VDDQ + 1.0 V with a pulse width of 20% of tKC min (3 ns max)
DC RECOMMENDED OPERATING CONDITIONS (Ta = 0 to 70C)
SYMBOL VDD VDDQ VIH VIH1 VIL VIL1 PARAMETER Power Supply Voltage Output Buffer Power Supply Voltage Input High Voltage Input High Voltage for MODE pin Input Low Voltage Input Low Voltage for MODE and NU pins MIN 3.135 3.135 2.0 VDD - 0.3 -0.3* -0.3 TYP. 3.3 3.3 VDD 0.0 MAX 3.465 3.465 VDD + 0.3** VDD + 0.3 0.8 0.3 UNIT V V V V V V
*: -0.7 V with a pulse width of 20% of tKC min (3 ns max) **: VDD + 0.7 V with a pulse width of 20% of tKC min (3 ns max) Note: NU pin must be low or not connected. You must not apply a voltage of more than 0.8V to the NU.
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DC CHARACTERISTICS (Ta = 0 to 70C, VDD = VDDQ = 3.3 V 5 %)
SYMBOL IIL INU ILO PARAMETER Input Leakage Current Input Current (NU pin) Output Leakage Current Output High Voltage VIN = 0 to VDD VIN = 0 to 0.3 V Device Deselected or Output Deselected, VOUT = 0 to VDDQ IOH = -8 mA IOH = -100 A IOL = 8 mA IOL = 100 A 22(225 MHz) IDDO1 Operating Current Device Selected IOUT = 0 mA, All Inputs = VDD - 0.2 V/0.2 V Clock tKC Minimum 20(200 MHz) 16(167 MHz) 15(150 MHz) 22(225 MHz) IDDO2 Operating Current (idle) Device Deselected IOUT = 0 mA, All Inputs = VDD - 0.2 V/0.2 V Clock tKC Minimum Clock = VSS All Inputs = VIH or VIL Clock = VSS All Inputs = VDD - 0.2 V or 0.2 V ZZ VDD - 0.2 V All Inputs = VDD - 0.2 V or 0.2 V Clock tKC Minimum
CKE VIH All Inputs = VDD - 0.2 V or 0.2 V Clock tKC Minimum
TEST CONDITIONS
MIN -1 -1 -1 2.4 VDDQ - 0.2
TYP.
MAX 1
UNIT A A A
1
1 0.4
VOH
V
VOL
Output Low Voltage
V 0.2 TBD TBD mA TBD TBD TBD TBD mA TBD TBD 100 mA
20(200 MHz) 16(167 MHz) 15(150 MHz)
IDDS1 IDDS2
Standby Current (TTL level) Standby Current (MOS level) Standby Current (Snooze Mode)
10
mA
IDDS3
10
mA
IDDS4 Note:
Standby Current ( CKE Mode)
10
mA
Operating Current (IDDO1) is specified with 50% Read cycles and 50% Write cycles.
CAPACITANCE (Ta = 25C, f = 1 .0 MHz)
SYMBOL CIN CI/O CNU CMODE Note: PARAMETER Input Capacitance Input/Output Capacitance Input Capacitance of NU Input Capacitance of NODE TEST CONDITIONS VIN = GND VI/O = GND VNU = GND VMODE = GND MAX 5 7 10 10 UNIT pF pF pF pF
This parameter is periodically sampled and is not 100% tested.
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AC CHARACTERISTICS (Ta = 0 to 70C, VDD = VDDQ = 3.3 V 5 %)
TC55VDM518AFFN SYMBOL PARAMETER 22 (225MHz) MIN tKC tKH tKL tKQV tKQX tKQLZ tKQHZ tGQV tGQLZ tGQHZ tAS tDS tWS tCES tADVS tBWS tCKES tAH tDH tWH tCEH tADVH tBWH tCKEH tZS tZR tZHZ CLK Cycle Time CLK High Pulse Width CLK Low Pulse Width CLK High to Output Valid CLK High to Output Invalid CLK High to Output Low-Z CLK High to Output High-Z
OE Low to Output Valid OE Low to Output Low-Z OE High to Output High-Z
20 (200MHz) MIN 5.0 2.0 2.0 1.5 1.5 1.5 1.5 0 1.4 1.5 1.4 1.4 1.4 1.4 1.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 5 5 MAX 3.2 3.0 3.2 3.0 2
16 (167MHz) MIN 6.0 2.2 2.2 1.5 1.5 1.5 1.5 0 1.5 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 5 5 MAX 3.5 3.0 3.5 3.0 2
15 (150MHz) MIN 6.6 2.5 2.5 1.5 1.5 1.5 1.5 0 1.5 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 5 5 MAX 3.8 3.0 3.8 3.0 2
UNIT
MAX 2.8 2.8 2.8 2.8 2
4.4 2.0 2.0 1.5 1.5 1.5 1.5 0 1.4 1.4 1.4 1.4 1.4 1.4 1.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 5 5
Address Setup Time from CLK Data Setup Time from CLK
WE Setup Time from CLK
ns
CE Setup Time from CLK ADV Setup Time from CLK
BW Setup Time from CLK CKE Setup Time from CLK
Address Hold Time from CLK Data Hold Time from CLK
WE Hold Time from CLK
CE Hold Time from CLK ADV Hold Time from CLK
BW Hold Time from CLK CKE Hold Time from CLK
ZZ Standby Time ZZ Recovery Time ZZ to Output in High-Z
cycle
AC TEST CONDITIONS
PARAMETER Input Pulse Level Input Pulse Rise and Fall Time Input Timing Measurement Reference Level Output Timing Measurement Reference Level Output Load TEST CONDITION 3.0 V/ 0.0 V 1 V/ns (20%/80%)
Fig.1:AC test load
Fig.2:AC test load
3.3 V 295 I/O pin 50 217
I/O pin
Z0 = 50
1.5 V
CL = 20 pF 1.5 V
CL = 5 pF
(for Enable/Disable spec)
1.5 V As shown in Fig.1 and Fig.2
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TIMING DIAGRAMS
(1) READ CYCLE
Read Continue Read Continue Read Continue
Read
Read tKC tKH tKL
Deselect
Read
CLK tAH tAS Address A0 tADVH tADVS ADV tWH tWS
WE
A1 tADVH tADVS
A2
BW1 to BW2
tCKEH tCKES
CKE
tCEH tCES
CE
tCEH tCES
OE
tGQV tGQLZ I/O tKQLZ tKQV
tKQV tKQX Q0 Q1 Q1+1
tKQHZ tKQX Q1+2 tKQLZ tKQV Q2
: Don't Care : Indeterminate
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(2) WRITE CYCLE
Write Continue Write Continue Write Continue
Write
Write tKC tKH tKL
Deselect
Write
CLK tAH tAS Address A0 tADVH tADVS ADV tWH tWS
WE
A1 tADVH tADVS
A2
tBWH tBWS
BW1 to BW2
tCKEH tCKES
CKE
tCEH tCES
CE
tCEH tCES
OE
tDH tDS I/O D0 D1 D1+1 D1+2 Hi-Z D2
: Don't Care : Indeterminate
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(3) WRITE/READ CYCLE
Read Continue Write Continue
Write
Read tKC tKH tKL
Write
Read
Write
Read
CLK tAH tAS Address A0 A1 tADVH tADVS ADV tWH tWS
WE
A2
A3
A4
A5
tBWH tBWS
BW1 to BW2
tCKEH tCKES
CKE
tCEH tCES
CE
tGQV
OE
tDH tDS I/O D0 tKQLZ tKQV Q1
tGQHZ
tGQLZ
D2 tKQX tKQHZ
Q3
Q3+1
D4
D4+1
: Don't Care : Indeterminate
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(4) CLOCK IGNORE/DESELECT CYCLE
Clock Ignore Clock Ignore Deselect Deselect Deselect Continue Continue
Read
Read tKH tKC tKL
Read
Write
Read
CLK tAH tAS Address A0 tADVH tADVS ADV tWH tWS
WE
A1
A2
A3
A4
tBWH tBWS
BW1 to BW2
tCKEH tCKES
CKE
tCEH tCES
CE
tCEH tCES
I/O tKQLZ tKQV
Q0 tKQLZ tKQV
Q1
Q2 tKQX
D3
Q4 tKQX tKQHZ
tKQHZ
: Don't Care : Indeterminate
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(5) SNOOZE CYCLE
tKC tKH CLK tKL
ADV tZS ZZ tZR
All inputs Deselect or Read (except ZZ pin) tZHZ Dout
Deselect or Read
Normal
: Don't Care : Indeterminate Notes: 1. The 2 cycles immediately prior to a Snooze brought about by the ZZ pin must be Read or Deselect cycles. 2. Memory data is retained during Snooze cycles.
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Notes: 1. Do not apply opposite data polarity to the I/O pins when they are in the output state. 2. Output enable and output disable times are specified as follows using the output load shown in Fig.1.
(A)
tKQLZ , tKQHZ
CLK (See Note 1) (See Note 1)
ADV
CE , CE2 , CE2
tKQLZ 0.2 V
tKQHZ 0.2 V VALID DATA OUT
Dout (See Note 2) 0.2 V
(See Note 3)
0.2 V
Notes: 1. Input states are defined in the Synchronous Input Truth Table. 2. If the device was previously deselected, when the device is selected, the output remains in a high impedance state in the present clock cycle regardless of OE because of the output enable delay register. Valid data appears in the second clock cycle when OE is low. 3. When the device is deselected, the output goes into a high impedance state in the next clock cycle regardless of OE .
(B)
tGQLZ , tGQHZ , tZZHZ
OE , ZZ
tGQLZ Dout 0.2 V 0.2 V VALID DATA OUT
tZZHZ tGQHZ 0.2 V
0.2 V
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VDDQ = 2.5 V Interface specification DC RECOMMENDED OPERATING CONDITIONS (Ta = 0 to 70C)
SYMBOL VDD VDDQ VIH VIH1 VIL VIL1 PARAMETER Power Supply Voltage Output Buffer Power Supply Voltage Input High Voltage for Address and Control pins Input High Voltage for I/O pins Input High Voltage for MODE pin Input Low Voltage Input Low Voltage for MODE and NU pins MIN 3.135 2.375 1.7 1.7 VDD - 0.3 -0.3* -0.3 TYP. 3.3 2.5 VDD 0.0 MAX 3.465 2.9 VDDQ + 0.3** VDDQ + 0.3*** VDD + 0.3 0.7 0.3 UNIT V V V V V V
*: -0.7 V with a pulse width of 20% of tKC min (3 ns max) **: VDD + 0.7 V with a pulse width of 20% of tKC min (3 ns max) ***: VDDQ + 0.7 V with a pulse width of 20% of tKC min (3 ns max) Note: NU pin must be low or not connected. You must not apply a voltage of more than 0.8V to the NU.
DC CHARACTERISTICS (Ta = 0 to 70C, VDD = 3.3 V 5 %, VDDQ = 2.375 V to 2.9 V)
SYMBOL IIL INU ILO PARAMETER Input Leakage Current Input Current (NU pin) Output Leakage Current Output High Voltage TEST CONDITIONS VIN = 0 to VDDQ VIN = 0 to 0.3 V Device Deselected or Output Deselected, VOUT = 0 to VDDQ IOH = -2 mA IOH = -100 A IOL = 2 mA IOL = 100 A 22 (225 MHz) IDDO1 Operating Current Device Selected IOUT = 0 mA, All Inputs = VDDQ - 0.2 V/0.2 V Clock tKC Minimum 20 (200MHz) 16 (167MHz) 15 (150MHz) 22 (225 MHz) IDDO2 Operating Current (idle) Device Deselected IOUT = 0 mA, All Inputs = VDDQ - 0.2 V/0.2 V Clock tKC Minimum Clock = VSS All Inputs = VDDQ - 0.2 V or 0.2 V ZZ VDD - 0.2 V All Inputs = VDDQ - 0.2 V or 0.2 V Clock tKC Minimum
CKE VIH All Inputs = VDDQ - 0.2 V or 0.2 V Clock tKC Minimum
MIN -1 -1 -1 1.7 VDDQ - 0.2
TYP.
MAX 1
UNIT A A A
1
1 0.7
VOH
V
VOL
Output Low Voltage
V 0.2 TBD TBD mA TBD TBD TBD TBD mA TBD TBD 20 mA
20 (200MHz) 16 (167MHz) 15 (150MHz)
IDDS2
Standby Current (MOS level) Standby Current (Snooze Mode)
IDDS3
20
mA
IDDS4 Note:
Standby Current ( CKE Mode)
20
mA
Operating Current (IDDO1) is specified with 50% Read cycles and 50% Write cycles.
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AC CHARACTERISTICS (Ta = 0 to 70C, VDD = 3.3 V 5 %, VDDQ = 2.375 V to 2.9 V)
TC55VDM536AFFN SYMBOL PARAMETER 22 (225MHz) MIN tKC tKH tKL tKQV tKQX tKQLZ tKQHZ tGQV tGQLZ tGQHZ tAS tDS tWS tCES tADVS tBWS tCKES tAH tDH tWH tCEH tADVH tBWH tCKEH tZS tZR tZHZ CLK Cycle Time CLK High Pulse Width CLK Low Pulse Width CLK High to Output Valid CLK High to Output Invalid CLK High to Output Low-Z CLK High to Output High-Z
OE Low to Output Valid OE Low to Output Low-Z OE High to Output High-Z
20 (200MHz) MIN 5.0 2.0 2.0 1.5 1.5 1.5 1.5 0 1.4 1.5 1.4 1.4 1.4 1.4 1.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 5 5 MAX 3.2 3.0 3.2 3.0 2
16 (167MHz) MIN 6.0 2.2 2.2 1.5 1.5 1.5 1.5 0 1.5 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 5 5 MAX 3.5 3.0 3.5 3.0 2
15 (150MHz) MIN 6.6 2.5 2.5 1.5 1.5 1.5 1.5 0 1.5 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 5 5 MAX 3.8 3.0 3.8 3.0 2
UNIT
MAX 2.8 2.8 2.8 2.8 2
4.4 2.0 2.0 1.5 1.5 1.5 1.5 0 1.4 1.4 1.4 1.4 1.4 1.4 1.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 5 5
Address Setup Time from CLK Data Setup Time from CLK
WE Setup Time from CLK
ns
CE Setup Time from CLK ADV Setup Time from CLK
BW Setup Time from CLK CKE Setup Time from CLK
Address Hold Time from CLK Data Hold Time from CLK
WE Hold Time from CLK
CE Hold Time from CLK ADV Hold Time from CLK
BW Hold Time from CLK CKE Hold Time from CLK
ZZ Standby Time ZZ Recovery Time ZZ to Output in High-Z
cycle
AC TEST CONDITIONS
PARAMETER Input Pulse Level Input Pulse Rise and Fall Time Input Timing Measurement Reference Level Output Timing Measurement Reference Level Output Load TEST CONDITION 2.5 V/ 0.0 V 1 V/ns (20%/80%)
Fig.1:AC test load
Fig.2:AC test load
2.5 V 295 I/O pin 50 217
I/O pin
Z0 = 50
1.25 V
CL = 20 pF 1.25 V
CL = 5 pF
(for Enable/Disable spec)
1.25 V As shown in Fig.1 and Fig.2
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PACKAGE DIMENSIONS
LQFP100-P-1420-0.65B
Unit: mm
Weight:
g (typ)
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Data sheet Revision History
Release Date
2002-09-30 2002-12-04
History
1. New Datasheet Release 1. AC parameter change tKQV (MAX) from 3.8 ns to 3.5 ns at 16 (167 MHz) 2. DC parameter change at 2.5 V interface IDDS2,3,4 (MAX) from 10 mA to 20 mA 3. DC test condition change at IIL, IDDO1, IDDO2, IDDS2, IDDS3, IDDS4 1. AC parameter change tGQHZ (MIN) from 1.5 ns to 0 ns 2. AC parameter change at snooze mode Add parameter : tZS, tZR, tZHZ Delete parameter : tZZ, tZZR, tZZHZ, tZZLZ
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RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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